Time Slot Interchange (TSI) facilities are used in time division multiplex switching systems to interconnect a calling station served by a first system time slot to a called station served by a second system time slot. This permits a common signal path to serve concurrently a plurality of calls by time sharing the use of the common path. Each call connection is granted exclusive use of the path for the time interval defined by the system time slots associated with the connection.
A basic version of a time slot interchanger comprises a time slot driven RAM which is written with call information during a first time slot under control of a first source of address information and which is read out during a second time slot under control of a second source of address information. Each system time slot is associated with a unique RAM location as well as with a unique station served by the system. PCM encoded " speech" signals generated at a first stat:on involved on a call are written into the associated RAM location during the occurrence of the time slot associated with the first station with the output of the system's time slot counter being used as the addressing signal source. This PCM call information is transferred to a second station involved on the call during the occurrence of the system time slot assigned to the second station. This transfer is effected by applying the output of the system time slot counter to a translation RAM which generates an output signal identifying the time slot serving the first station. This generated time slot number is applied as addressing information to the time slot driven RAM which reads out the call information from its addressed location and applies the readout information to facilities that extend it to the second station.
U.S. Pat. No. 4,112,258 issued Sept. 5, 1978 to H. G. Alles discloses an improved time slot interchanger that comprises a program controlled signal processor. In addition to performing a conventional time slot interchange function, the Alles TSI can insert a specified gain or loss into the interchange of any call signal. The Alles TSI also provides conferencing facilities. These facilities include the use of a single register operating as an accumulator for generating and storing the conferee sum and difference signals required in the serving of conference calls.
In most conference circuits, signals are generated that represent the summation of the speech signals of all conference parties. Signals are also generated which represent the difference between the summation signal and the signal contributed by each conferee. A unique difference signal is generated for each party so that the resultant signal transmitted to the party represents the summation signal less the speech signal contributed by the party. This permits each party to hear only the other conferees, and not his or her own speech, in the receiver of the station handset.
The signal summation operation and the generation of the various difference signals are effected in Alles by the repeated use of the single accumulated register as his signal processor executes the instructions stored in the controlling memory of his TSI. The provision of a single accumulator register for the concurrent serving of all conference calls requires that the plurality of instructions associated with a conference call be contiguous to one another within the memory. This is necessary so that the required summation and difference signals for a first conference call can be generated sequentially and transmitted to the conferee parties before the signal processor executes instructions for other conference calls. If the program instructions for a first conference call were not contiguous, information in the accumulator RAM pertaining to the first call would be overwritten with information pertaining to a second conference call. The subsequent execution of an instruction associated with the first call, and involving the use of the accumulator, would generate meaningless information since the accumulator would then contain information pertaining to the second call.
The provision of a single accumulator RAM in Alles imposes programming restraints since the establishment and serving of each new conference call requires the Alles system controller to communicate with the TSI memory to determine that there are currently available a sufficient number of contiguous idle memory locations to serve the new call. The number of contiguous memory locations required varies with the number of parties involved on each call. A conventional two party connection may require six contiguous locations, a three party conference call requires eight contiguous locations, a four party conference call requires twelve contiguous locations, etc.
Since the number of memory locations required to serve a call varies, the Alles system requires "overhead" operations to sometimes relocate the unused and the used locations so that as many unused locations as are required by a connection may be contiguous to one another. This permits maximum flexibility to be achieved in allocating TSI memory locations to serve newly initiated calls.
Another characteristic of the Alles TSI is that the instructions provide limited functions suitable to a general purpose signal processor. This results in the need for many instructions to achieve a connection, six for a two party connection and so forth, as mentioned above. For a fixed system frame interval and a given instruction execution speed, only a fixed number of instructions can be executed per frame. So the requirement for many instructions per connection means that fewer simultaneous connections can be provided by the TSI.
From the above, it can be seen that although the Alles TSI represents an improvement over the conventional time slot driven RAM TSI, the use of a single accumulator for serving conference calls results in undesirable programming complexity. This complexity results in system overhead operations that decrease the throughput of the processor controlling the Alles TSI. Also, the need for many instructions per connection means that costly high speed designs are required to achieve a large number of simultaneous connections.